description designed for pulse width modulated (pwm) current control of single phase brushless fans, the A4930 minimizes external component count and integrates all the key features required for high-current fans. internal synchronous rectification control circuitry is provided to improve power dissipation in the external mosfets during pwm operation. internal circuit protection includes thermal shutdown with hysteresis, rotor lock, and dead time protection. the A4930 is supplied in a 0.90 nominal overall height, 5 mm 5 mm, 28-pin qfn with exposed thermal pad, (suffix et). it is lead (pb) free with 100% matte tin leadframe plating. 4930-ds, rev. 1 features and benefits ? synchronous rectification for low power dissipation ? drives four n-channel mosfets ? internal uvlo and thermal shutdown circuitry ? hall element input ? pwm current limiting ? dead time protection ? fg output ? rd output ? lock detect protection ? high v bb absolute maximum ? soft start single phase fan pre-driver package: 28-pin qfn with exposed thermal pad (suffix et) functional block diagram A4930 approximate size 5v gate drive vcp vreg8 hp hn hall hall hall sense vbb vcp cp1 cp2 vreg5 ss +12v fgo lock detect cld smin control logic cdel cpwm rd pwm sin vreg5 ghb sa hp hn vreg5 vreg5 charge pump gha gla sb glb vref /5 vreg8 8v 470 pf 0.1 f 0.1 f 0.1 f0.1 f 0.1 f 51 k vref gnd gnd 0.47 f 1.5v 3.5v 500 0.1 f 10 f 0.22 f 5 k 8.2 k 5 k 1.24 k 100 m fan hall
single phase fan pre-driver A4930 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number ambient operating temperature, t a (c) packing A4930gettr-t ?40 to 105 1500 pieces per 7-in. reel A4930mettr-t ?20 to 105 thermal characteristics may require derating at maximum conditions characteristic symbol test conditions a value units package thermal resistance (junction to ambient) r ja 4-layer pcb based on jedec standard 32 oc/w 2-layer pcb with 0.7 in. 2 copper area 65 oc/w package thermal resistance (junction to case) r jc 20 b oc/w a additional thermal information available on allegro website. b estimated. absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 36 v hall input v hx ?0.3 to 6 v logic input voltage range v in ?0.3 to 6 v operating temperature range t a range g ?40 to 105 oc range m ?20 to 105 oc junction temperature t j (max) 150 oc storage temperature range t stg ?55 to 150 oc 25 50 75 125 100 150 temperature (c) power dissipation, p d (m w) 4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 power dissipation versus ambient temperature (r q ja = 32 oc/w) (r q ja = 65 oc/w)
single phase fan pre-driver A4930 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? electrical characteristics 1 valid at t a = 25c, v bb = 12 v, unless noted otherwise characteristic symbol test conditions min. typ. 2 max. units load supply voltage range v bb operating 8 12 36 v motor supply current i bb f pwm < 30 khz, c load = 1000 pf ? 5 7 ma vreg5 v 5 i load = 10 ma 4.7 5 5.3 v vreg5 current limit i reg5 15 ? ? ma vreg5 load regulation v reg5 i reg5 = 1 to 10 ma ? 12 30 mv control logic logic input voltage v in(1) 2??v v in(0) ? ? 0.8 v pwm pin input current i in(0) v in = 0, 50 k pull-up ? ?100 ? a other logic pin input current i in(1) v in = 3.3 ? ?34 ? a gate drive high side gate drive output v ghx relative to v bb , vbb = 12 v 7 ? ? v low side gate drive output v glx 7 ? 8.5 v gate drive current turn-on i g ghx = glx = 4 v ? 20 ? ma gate drive pulldown r ds ? 40 ? dead time t dead 700 1000 1300 ns control soft start time t ss c ld = 0.47 f ? 300 ? ms internal pwm frequency f pwm c pwm = 470 pf 15 21 27 khz cpwm output voltage v pp c pwm = 470 pf ? 2 ? v cpwm low threshold v lo ? 1.5 ? v cpwm high threshold v hi ? 3.5 ? v sin input impedance z in ? 200 ? k protection thermal shutdown temperature t jtsd ? 165 ? c thermal shutdown hysteresis t jtsdhys ? 15 ? c
single phase fan pre-driver A4930 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vbb undervoltage lockout enable threshold v bbuv rising v bb ? 7.5 7.85 v vbb undervoltage lockout hysteresis v bbuvhys 0.3 0.8 ? v vcp undervoltage lockout enable threshold v cpuv relative to v bb , v bb rising ? 5.4 ? v lock detect on-time t ldon c ld = 0.1 f ? 1 ? s lock detect off-time t ldoff c ld = 0.1 f ? 15 ? s hall logic hall input current i hall v in = 1.2 v ?1 0 1 a common mode input range v cmr 0.2 ? 3 v ac input voltage range v hall 60 ? ? mv p-p hall threshold v th difference in halls at fg transition ? 10 ? mv hysteresis width v hys 5 20 35 mv pulse reject filter t cd 12 3 s commutation delay v pu r cdel = 50 k ? 50 ? mv fg and rd outputs output saturation voltage v ol i = 2 ma ? 0.27 0.4 v leakage current v oh v = 5 v ? ? 1 a 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. electrical characteristics 1 (continued) valid at t a = 25c, v bb = 12 v, unless noted otherwise characteristic symbol test conditions min. typ. 2 max. units
single phase fan pre-driver A4930 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vreg5 this pin should be decoupled with a 0.1 f capacitor to ground. vreg5 can supply up to 15 ma, which can used to power the external hall element. vreg8 this pin should be decoupled with a 0.1 f capacitor to ground. vreg8 is used to power the low-side gate drive circuits. charge pump the charge pump is used to generate a supply above v bb to drive the high-side mosfets. the vcp voltage is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. lock detect the ic detects a locked rotor condition by checking to ensure that the fg output signal is continuously changing. the length of time allowed for a stoppage before evaluating a locked condition, t ld , is set by capacitor connected to cld pin. c ld pro- duces a triangle waveform with a frequency that is linearly related to the capacitor value. the definition of t ld is defined as 8 cycles of this triangle waveform, and its value can be calculated as: t ld = c ld (10 s / f) . (1) if an fg transition is not detected within t ld , the ic will disable the appropriate source driver and hold both sink drivers on. the circuit will automatically retry with a 15:1 ratio of off-time to on- time. an rd pin logic high indicates this fault condition. current limit and soft start to minimize demand on the power supply, peak current is controlled. initially, with the fan at a stand-still, the turn-on of the bridge results in current rising according to the l/r time constant of the motor. to prevent over- stress, this peak current is regulated by an internal pwm control circuit. when the outputs of the full-bridge are turned on, current increases in the motor winding until it reaches a value given by: i trip = v ref / 5 r sense . (2) the r sense value should be chosen to keep the peak sense voltage within the range of 200 to 500 mv, according to the relationship: r sense < 500 mv / i trip . (3) at the trip point, the sense comparator resets the source enable latch, turning off the source driver. at this point, load inductance causes the current to recirculate for 50 s. a soft start capacitor, css, can be connected to the ss pin to set the rate for slowly ramping-up the load current to the maximum value, according to the relationship: t ss = ( c ss v ref ) / 3.3e?6 . (4) in this case the current limit will likely not be achieved and there will be less demand on the input power supply. if this feature is not utilized, the ss pin should be left open. synchronous rectification when a pwm off-cycle is triggered, load current recirculates. the A4930 synchronous rectification feature turns on the appropriate mosfets during current decay, and effectively shorts out the body diodes of the low r ds(on) driver. tsd if the die temperature exceeds approximately 165c, the outputs will be disabled until the internal temperature falls below a hysteresis level of 15c. shutdown in the event of a fault due to excessive junction temperature, or low voltage on vcp or vbb, the outputs of the device are disabled until the fault condition is removed. at power-up the uvlo circuit disables the drivers until the uvlo threshold is reached. cpwm this capacitor sets the frequency of the internal pwm circuit. the value is typically from 15 to 30 khz. pwm the ic accepts a direct input pwm signal with a level in the range from 0 to 6 v. the duty cycle, dc, of the input to this pin is converted to an analog voltage that is output on the sin terminal as follows: v sin = 3.5 v ?2 dc . (5) if the pwm input is not used, then leave this pin open circuit. direct external pwm control can be utilized by applying the signal to the sin input (refer to the applications information sec- tion). this can be implemented to create different pwm input to pwm output transfer functions. functional description
single phase fan pre-driver A4930 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sin an analog voltage input to this pin sets the duty cycle applied to the fan winding. for temperature-based systems, connect sin to a thermistor output. for systems with direct input to the pwm pin, the pin should be decoupled with a 0.1 f capacitor. if vari- able fan speed is not required, for 100% duty cycle, connect this pin to gnd. the input impedance is 200 k (referenced to a 3.5 or 1.5 v rail). smin an analog voltage input to this pin sets the minimum speed duty cycle to the fan winding. the pwm comparator chooses either sin or smin to determine the output duty cycle, which- ever is set to a lower voltage. for 100% duty cycle applications, connect this pin to gnd. cdel a resistor connected between this pin and gnd sets the level at which the A4930 switches to slow decay mode in advance of the hall zero crossing as shown here: v cdel = (2950 / r cdel ) ? 7 mv . (mv) (6) the resistor should be 25 to 100 k . if this feature is not used, the cdel pin should be pulled up to v reg5 with a 5 k resistor. sa sb t cdel hp v cdel (1) v cdel (2) v th (1) v th (1) = v hp C v hn = 10 mv (typical) v th (2) = v hn C v hp = 10 mv (typical) v hys = v th (1) + v th (2) = 20 mv (typical) v th (2) 0 hn fg ld
single phase fan pre-driver A4930 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information overvoltage in a typical fan application, there is a blocking diode that prevents currents from flowing back out of the fan assembly to the 12 v supply. when the fan commutates before the current has decayed to zero, the current charges up the vbb bypass capacitor. the larger the bypass capacitor, the less the voltage overshoot. typically, a clamp diode is required to dissipate energy from the inductive kickback to avoid exceeding the maximum rating for v bb , 36 v. layout small form factor pcbs present a layout challenge for the application. the layout would be restricted by the placement of the hall element, the location of the motor connectors, and the common requirement that all components be placed on one side of the pcb. for optimum results, consider the following recom- mendations: ? place the external mosfet bridge close to the power connec- tor. the bridge includes two dual n-channel mosfets, a sense resistor, and a power supply capacitor. this will keep the large current flows in one area of the pcb and avoid ground loop problems. ? keep the sense connection to the power bridge as short as pos- sible. this can be achieved by positioning the mosfets next to each other, and by connecting the source of the sink side mos- fets via a short trace, preferably on the surface of the pcb, under the mosfets. a short trace here would minimize voltage spikes due to inductance in the path, where currents switch at high di/dt. ? place the power traces from the mosfets to the motor con- nector on the opposite side of the pcb. if possible, on that side isolate the power traces by ground traces in order to minimize interference with other signal traces due to the high dv/dt of the power traces. ? locate the A4930 to minimize the length of the ghx/glx/sx traces to the power stage. ? connect the gnd pins of the A4930 to the exposed pad. use vias under the ic case to connect the exposed pad to the ground plane on the opposite face of the pcb. external pwm refering to the figure below, if external pwm control is being used, the high voltage level is set by r1, r2, and r3. the low voltage level is set by r1 and r3. control logic 5 k 10 k 8.2 k pwm cpwm 0.47 f 0.1 f r1 r2 pwm duty in r3 sin smin vreg5 + ? pwm control using external pwm input
single phase fan pre-driver A4930 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list number name description number name description 1 vreg5 regulator decoupling terminal 16 glb low-side drive for external n-channel mosfet 2 cld capacitor to set lock detect time 17 gla low-side drive for external n-channel mosfet 3 fg fg output, fan speed indicator (open drain) 18 vreg8 gate drive supply 4rd rd output, high for locked rotor condition (open drain) 19 sb high-side source connection 5 hp hall input positive 20 ghb high-side drive for external n-channel mosfet 6 hn hall input negative 21 sa high-side source connection 7 cdel commutation delay 22 gha high-side drive for external n-channel mosfet 8 pwm pwm input 23 gnd ground 9 cpwm capacitor to set internal frequency 24 cp1 charge pump capacitor terminal 10 sin speed analog input/adjusted pwm output 25 cp2 charge pump capacitor terminal 11 smin minimum speed analog input 26 vcp reservoir capacitor terminal 12 ss connection for soft start capacitor 27 vbb supply voltage 13 vref current limit setpoint 28 nc not connected 14 gnd ground ? pad thermal pad, connect to gnd plane with vias to bottom of pcb 15 sense sense resistor connection pad 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 nc vbb vcp cp2 cp1 gnd gha pwm cpwm sin smin ss vref gnd sa ghb sb vreg8 gla glb sense vreg5 cld fg rd hp hn cdel
single phase fan pre-driver A4930 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2008-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com package et 28-pin qfn with exposed thermal pad 0.25 +0.05 ?0.07 0.55 +0.20 ?0.10 0.50 0.90 0.10 c 0.08 29x seating plane c a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220vhhd-1) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p500x500x100-29v1m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 28 2 1 a 28 1 2 pcb layout reference view b 3.15 3.15 3.15 3.15 0.30 1 28 0.50 1.15 4.80 4.80 c 5.00 0.15 5.00 0.15 d d coplanarity includes exposed thermal pad and terminals
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